SY21219 6 A synchronous buck: 5 V at 6 A from up to 30 V
Overview
A 12 V to 5 V buck converter built around the SY21219, a 6 A synchronous buck that accepts 4.5–30 V and uses constant on-time, ripple-based control at about 500 kHz in a QFN2×3-14 package. It has more supporting circuitry than the smaller parts: an external bootstrap capacitor, an internal 3.3 V supply with its own capacitor, a power-good output, and an optional feedforward network. This recipe takes the circuit from Silergy's datasheet, adds the reasoning behind each part value, and works the numbers for 12 V in. It also covers how the part regulates, how to set other output voltages, and what the datasheet says about layout and thermal design.
Reference circuit
| Ref | Part | Description | Maker |
|---|---|---|---|
| U1 | SY21219 | 6 A synchronous buck regulator, QFN2×3-14 (ordering code SY21219WYQ) | Silergy |
| CIN1 | 47 µF, 50 V electrolytic | Bulk input capacitor; damps ringing when VIN arrives on long leads | |
| CIN2 | GRM31CR61H106KA12L | 10 µF, 50 V, X5R, 1206. Input decoupling, placed at the IN and GND pins | Murata |
| CIN3 | GRM188R61H104KA93D | 0.1 µF, 50 V, X5R, 0603. High-frequency input decoupling | Murata |
| CBS | GRM188R61H104KA93D | 0.1 µF, 50 V, X5R, 0603. Bootstrap capacitor, BS to LX | Murata |
| COUT1, COUT2, COUT3 | GRM31CR61C226ME15L | 22 µF, 16 V, X5R, 1206 each. Output capacitors (three in parallel, 66 µF) | Murata |
| CVCC | GRM188R61C225KE15D | 2.2 µF, 16 V, X5R, 0603. Decouples the internal 3.3 V supply (VCC), returned to AGND | Murata |
| CFF | GRM1885C1H221JA01D | 220 pF, 50 V, C0G, 0603. Feedforward capacitor, in series with RFF across RH | Murata |
| L | PCMB104T-4R7MS | 4.7 µH, 8.5 A inductor | Cyntec |
| RH | 100 kΩ, 1%, 0603 | Upper feedback resistor | |
| RL | 13.7 kΩ, 1%, 0603 | Lower feedback resistor; sets the 5 V output | |
| RFF | 1 kΩ, 1%, 0603 | Feedforward resistor, in series with CFF. Shown as optional in the datasheet figure | |
| RENH | 10 kΩ, 1%, 0603 | Enable resistor from VIN to EN | |
| RENL | 1 MΩ, 1%, 0603 | Enable resistor from EN to ground | |
| RPG | 100 kΩ, 1%, 0603 | Power-good pull-up from PG to VIN |
Design requirements
| What | The reference circuit |
|---|---|
| Input voltage | 4.5–30 V (the range of the part; absolute maximum 31 V) |
| Output | 5 V, up to 6 A (the part itself adjusts from 0.6 V to 24 V) |
| Switching frequency | About 500 kHz (425–575 kHz), pseudo-constant |
| Control | Constant on-time with ripple-based feedback; PFM at light load |
| Feedback reference | 0.6 V (0.591–0.609 V over −40 to 125 °C) |
| Soft-start | About 1 ms (0.7–1.3 ms), and it can start into a pre-biased output |
| Duty cycle | Up to 98% open loop; 100% with an external supply across BS–LX |
| Power good | Open drain; released while the output is within about 90% to 120% of its set value |
| Package | QFN2×3-14 |
The datasheet gives one reference circuit, for 5 V, a table of component values for 1.2, 3.3, 5 and 12 V, and a second table of feedforward values by output capacitance. It doesn’t name a nominal input voltage, so the worked example below uses 12 V, with 30 V, the top of the range, as the worst case for ripple and peak current. The datasheet’s own on-time example and its efficiency plots go up to 28 V, but its operating range is 4.5–30 V.
How it works
The SY21219 is a synchronous buck regulator with both power switches inside a QFN2×3-14 package. It regulates with constant on-time, ripple-based control. Each on-time is a fixed ratio, tON = (VOUT ÷ VIN) ÷ fSW. The datasheet says the chip derives this internally, without the dedicated output-voltage connection that older constant on-time designs need. The datasheet’s example is 5 V from 28 V at 500 kHz, which gives 357.14 ns. A new on-time starts when the feedback voltage, plus a virtual ramp the chip builds internally to imitate the inductor’s ripple, falls below the 0.6 V reference. It starts only if the minimum off-time (100 ns) has passed and the bottom switch’s current is below its limit. The virtual ramp is what lets the loop stay stable with low-ESR ceramic output capacitors, so no external compensation is needed.
There is no clock, so after a load step the top switch can turn on almost immediately, and the response is fast. The datasheet says there is no limit on low duty cycle: when the on-time gets close to its 50 ns minimum, the switching frequency is reduced as needed. At high duty cycle, as for a low input voltage, the on-time is stretched. If FB is still below the reference at the normal on-time and the duty cycle is above about 27%, the on-time is extended; the stretch is disabled below about 17% duty or when FB is under the UVP threshold. The datasheet quotes 98% open-loop duty, not counting the drops across the switches and inductor, and says 100% duty is possible if an external supply of more than 2.2 V is added across BS–LX.
At light load the part switches to pulse-frequency modulation (PFM). Once the load falls below half the inductor ripple current, IOUT = VOUT × (1 − D) ÷ (2 × fSW × L), the bottom switch turns off when its current reaches about zero, so no current flows backwards, and the controller waits to start another on-time until the output needs one, so the switching frequency falls with the load. In this circuit at 12 V in, with a 4.7 µH inductor, that crossover is about 0.62 A. Above it, the part runs in continuous conduction at nearly constant frequency. The datasheet notes that under deep light load or no load the frequency can fall below the audible limit, which matters in audio equipment.
EN is a precise-threshold input: the part turns on when EN rises above 1.2 V (typical; 1.08–1.32 V) and off when it falls below 1.0 V (0.9–1.1 V). Input under-voltage lockout keeps switching off until VIN passes 4.4 V (maximum), with 0.3 V of hysteresis. The output then ramps in about 1 ms. If the output is already pre-biased, both switches stay off until the soft-start ramp rises above the sensed output.
An internal linear regulator makes a 3.3 V supply, VCC, for the gate drivers and control logic, and needs a 2.2 µF ceramic capacitor. A 0.1 µF bootstrap capacitor between BS and LX supplies the top switch’s gate drive.
The power-good pin (PG) is an open-drain output watching the feedback voltage with a window comparator. It goes high about 200 µs after FB rises past 90% of the reference, goes low about 40 µs after FB falls below 85% or rises above 120%, and recovers from an over-voltage at 115%. After VIN comes up and the internal supply is ready, PG is driven low until the output is ready. Pull it up through a resistor, such as 100 kΩ, to VIN or another supply.
When the part shuts down, because of low VIN, EN or a fault, a discharge MOSFET in parallel with the bottom switch pulls the output down, about 80 mA at 5 V out, even with no load.
Current limiting works on both switches. The top switch turns off at its peak limit (9 A typical). The bottom switch has a valley limit (6 A typical): the next on-time is inhibited until the inductor current falls below it, so the output current limit is the valley limit plus half the ripple, ILMT,OUT = ILMT,BOT + ΔIL ÷ 2. If the output stays below about 50% of its set point for about 40 µs, the part enters hiccup mode, 2 ms on and 6 ms off, and recovers on its own when the fault is removed. Over-temperature protection shuts the part down at 150 °C and restarts it once it has cooled by about 15 °C.
Choosing the components
Output voltage
The output is set by two resistors: VOUT = 0.6 V × (1 + RH ÷ RL). The datasheet recommends 1 kΩ to 1 MΩ for both, to keep light-load current low. With RH = 100 kΩ and a 5 V target, RL = 0.6 ÷ (5 − 0.6) × 100 kΩ = 13.64 kΩ, and the nearest 1% value, 13.7 kΩ, gives 4.980 V nominal. With the reference’s tolerance (0.591–0.609 V) the output lands between 4.905 V and 5.054 V, before the resistors’ own tolerance is added.
Inductor
Choose the inductance for a ripple current of about 40% of the maximum load at the highest input voltage: L = VOUT × (1 − VOUT ÷ VIN,MAX) ÷ (fSW × IOUT,MAX × 0.4). For 5 V, 30 V in, 6 A and 500 kHz that gives 3.47 µH, and the datasheet uses 4.7 µH, which gives 30% ripple at 30 V and 21% at 12 V. The part tolerates a wide range of ripple, so the final value can differ from the calculation with little effect.
Two more checks apply. The saturation current must exceed the peak current, ISAT > IOUT,MAX + VOUT × (1 − VOUT ÷ VIN,MAX) ÷ (2 × fSW × L), which is 6.89 A here, and the PCMB104T-4R7MS is listed at 8.5 A. And the winding resistance (DCR) should be below 50 mΩ for good efficiency, and the core loss at 500 kHz should be low enough for the efficiency you need.
Output capacitor
Use an X5R or better ceramic rated for 16 V, with at least 10 µF. The reference circuit uses three 22 µF capacitors in parallel (66 µF), which is also what the datasheet’s performance plots use. Output ripple has two parts: the inductor ripple current across the capacitor’s ESR (ΔIL × ESR), and the charge on the capacitance (ΔIL ÷ (8 × COUT × fSW)). Add them for a total. Ceramic capacitance falls as the DC voltage across it rises, so measured ripple is usually higher than the calculation; read the effective capacitance off the capacitor’s DC-bias curve and recalculate.
Input capacitor
The datasheet recommends an X5R or better ceramic rated 50 V, 10 µF or more, as close as possible to the IN and GND pins with the smallest possible loop. It also says the voltage rating should be at least 20% above the highest input voltage, which is 36 V at 30 V in. The datasheet also recommends a 0.1 µF ceramic there to reduce high-frequency noise. The RMS current in the capacitor is IOUT × √(D × (1 − D)), at most IOUT ÷ 2 at 50% duty, so choose one with an RMS rating above half the load current, and add capacitors in parallel if the calculation needs it. The datasheet says capacitance matters less than RMS rating, and that a single 10 µF ceramic is enough for most applications. If VIN arrives over long wires, add bulk capacitance (electrolytic, tantalum or polymer) to damp the overshoot and ringing from the lead inductance. The reference circuit’s 47 µF electrolytic, CIN1, is that kind of bulk capacitor; the datasheet doesn’t say why it was included.
Bootstrap, VCC and feedforward
The bootstrap capacitor CBS is a 0.1 µF low-ESR ceramic between BS and LX. The VCC capacitor CVCC is a 2.2 µF low-ESR ceramic, and the datasheet’s schematic returns it to AGND. Keep both close to their pins (see Layout).
The integrated compensation is usually enough, but a series RC network, RFF and CFF, can be added across RH to speed up the load-transient response. The datasheet recommends RFF = 1 kΩ and CFF = 220 pF for most applications, and draws RFF as optional. With a large output LC, CFF can be increased so that FB receives enough ripple; for COUT above 500 µF it asks for RFF = 1 kΩ and CFF = 2.2 nF. The table under Other output voltages below gives the values for each inductor and output-capacitance range.
Enable
Don’t connect EN straight to VIN or another voltage source; the datasheet asks for a resistor between 1 kΩ and 1 MΩ. The reference circuit uses RENH = 10 kΩ and RENL = 1 MΩ, which puts EN at 99% of VIN, so the part starts when VIN passes its own under-voltage threshold and the divider only limits current. To start at a higher voltage, size the divider from the EN thresholds: VIN,start = VEN,R × (1 + RENH ÷ RENL), with 1.2 V rising and 1.0 V falling, typical. As an example, RENH = 562 kΩ with RENL = 100 kΩ starts the part at about 7.9 V and stops it at about 6.6 V.
Worked example: 12 V to 5 V
These numbers are calculated here from the datasheet’s formulas. The datasheet doesn’t list them, and nothing below was measured. They assume ideal switches and nominal component values, and the current limits are the typical values in the datasheet.
| Quantity | Value |
|---|---|
| Duty cycle at 12 V in | 41.7% (VOUT ÷ VIN) |
| On-time at 12 V and at 30 V in | 833 ns and 333 ns (the part’s minimum on-time is 50 ns) |
| Recommended inductance (40% ripple at 30 V) | 3.47 µH; the circuit uses 4.7 µH |
| Inductor ripple current at 12 V and at 30 V | 1.24 A (21% of full load) and 1.77 A (30%) |
| Peak inductor current, 30 V in, 6 A load | 6.89 A, below the 9 A top-switch limit |
| Valley inductor current, 30 V in, 6 A load | 5.11 A, below the 6 A valley limit |
| Output current limit (valley limit + ΔIL ÷ 2) at 12 V and at 30 V | About 6.6 A and 6.9 A |
| Inductor saturation rating needed | Above 6.89 A; the datasheet lists the PCMB104T-4R7MS as 8.5 A |
| Crossover to PFM at 12 V in | About 0.62 A |
| Input capacitor RMS current at 12 V in | 2.96 A (worst case 3.0 A at 50% duty) |
| Input ripple with one 10 µF ceramic at 12 V in | 292 mV (300 mV worst case), before DC-bias loss |
| Output ripple from the capacitance, 66 µF, at 12 V and at 30 V in | 4.7 mV and 6.7 mV, plus ΔIL × ESR |
The output current limit sits only a little above the 6 A rating. Using the datasheet’s formula and its typical 6 A valley limit, the output current limit comes to about 6.6 A at 12 V in and 6.9 A at 30 V in. The datasheet gives these limits only as typical values, with no minimum, so treat 6 A as a hard ceiling and don’t count on headroom for overloads.
The input ripple with a single 10 µF ceramic is large at 6 A. About 292 mV at 12 V in, before the capacitor loses capacitance under DC bias. The datasheet says a 10 µF ceramic is enough for most applications, and the reference circuit adds 47 µF of bulk capacitance and 0.1 µF of decoupling, but if your input has a ripple budget, add ceramic capacitance and check the RMS current rating, which is about 3 A here.
Other output voltages
The datasheet gives recommended values for four output voltages, all with RH = 100 kΩ. The last two columns are our additions: the nominal output that the listed resistors give, from the formula above, and the lowest input voltage at which each output is still possible. We estimate that last one as (VOUT + IOUT × (40 mΩ typical top-switch RDS(on) + 50 mΩ inductor DCR)) ÷ 0.98, using the 98% open-loop duty limit and a full 6 A load, never below the part’s own 4.5 V minimum. Leave margin.
| VOUT | RH | RL | CFF | Inductor | Nominal VOUT | Lowest VIN (estimate) |
|---|---|---|---|---|---|---|
| 1.2 V | 100 kΩ | 100 kΩ | 220 pF | 1.0 µH, PCMB104T-1R0MT | 1.200 V | 4.5 V (part minimum) |
| 3.3 V | 100 kΩ | 22.1 kΩ | 220 pF | 3.3 µH, PCMB104T-3R3MS | 3.315 V | 4.5 V (part minimum) |
| 5 V | 100 kΩ | 13.7 kΩ | 220 pF | 4.7 µH, PCMB104T-4R7MS | 4.980 V | 5.7 V |
| 12 V | 100 kΩ | 5.26 kΩ | 220 pF | 6.8 µH, PCMB104T-6R8MS | 12.007 V | 12.8 V |
For comparison, the datasheet’s efficiency plots start at 7.4 V in for the 5 V output and at 13.5 V in for the 12 V output.
The datasheet’s second table sets the feedforward network, RFF and CFF, for several inductors and ranges of total output capacitance:
| VOUT | L | COUT range | RFF | CFF |
|---|---|---|---|---|
| 1.2 V | 0.68 µH | 66–500 µF | 1 kΩ | 220 pF |
| 1.2 V | 1.0 µH | 66–500 µF | 1 kΩ | 220 pF |
| 1.2 V | 1.5 µH | 66–500 µF | 1 kΩ | 220 pF |
| 3.3 V | 2.2 µH | 66–500 µF | 1 kΩ | 220 pF |
| 3.3 V | 3.3 µH | 66–500 µF | 1 kΩ | 220 pF |
| 3.3 V | 4.7 µH | 66–100 µF | 1 kΩ | 220 pF |
| 3.3 V | 4.7 µH | 100–500 µF | 1 kΩ | 470 pF |
| 5 V | 3.3 µH | 66–500 µF | 1 kΩ | 220 pF |
| 5 V | 4.7 µH | 66–120 µF | 1 kΩ | 220 pF |
| 5 V | 4.7 µH | 120–500 µF | 1 kΩ | 470 pF |
| 5 V | 5.6 µH | 66–500 µF | 1 kΩ | 470 pF |
| 12 V | 4.7 µH | 66–120 µF | 1 kΩ | 220 pF |
| 12 V | 4.7 µH | 120–500 µF | 1 kΩ | 470 pF |
| 12 V | 5.6 µH | 66–120 µF | 1 kΩ | 220 pF |
| 12 V | 5.6 µH | 120–500 µF | 1 kΩ | 680 pF |
| 12 V | 6.8 µH | 66–220 µF | 1 kΩ | 470 pF |
| 12 V | 6.8 µH | 220–500 µF | 1 kΩ | 1000 pF |
The reference circuit’s 5 V, 4.7 µH row with 66 µF of output capacitance falls in the 66–120 µF range, so it takes 220 pF, which matches the schematic.
Layout
Silergy gives these layout rules, along with a suggested placement drawing. With a 6 A converter in a 2 × 3 mm package, layout decides how well the converter works and how hot it runs.
- Put the input capacitor close to the IN and GND pins, with the smallest loop, joined by a wide copper pour. Add the 0.1 µF ceramic there to reduce high-frequency noise.
- Connect the output capacitors’ negative terminals to GND with wide copper traces rather than vias, which the datasheet says gives better output-voltage accuracy and stability.
- Place the VCC capacitor close to the VCC pin, with a short, direct trace to the nearest AGND pin. Make one Kelvin connection between AGND and GND at the CVCC negative side, using multiple vias.
- Place the feedback network (RH, RL, RFF and CFF) as close to the FB pin as possible and keep the feedback line away from LX, BS and other fast signals. Take the feedback from the output capacitor with a Kelvin connection, not from the inductor’s output terminal.
- Keep the LX copper small to limit EMI, but wide enough to keep its resistance and inductance low.
- Put the BS capacitor on the same layer as the device, and keep the BS, LX and CBS path as short as possible.
- Don’t tie EN straight to VIN or another source; use a resistor between 1 kΩ and 1 MΩ.
- Put an adequate number of ground vias around the device, with several close to the GND pin, to carry heat away.
- Use a four-layer board with 2 oz copper. The datasheet strongly recommends it: wide IN and GND copper on the top and bottom layers, a solid ground layer in the middle to conduct heat and shield the signal layer, and signal lines on the second inner layer so the ground planes aren’t cut.
The datasheet’s thermal resistance (θJA) is 22 °C/W, measured on Silergy’s standard 8.5 × 8.5 cm four-layer thermal test board (2 oz copper traces to every pin, large unbroken 1 oz internal power and ground planes). The maximum power dissipation is PD,MAX = (TJ,MAX − TA) ÷ θJA with TJ,MAX = 125 °C, which the datasheet works out as 4.55 W at 25 °C, and it gives a derating curve against ambient temperature. It warns that matching that board’s performance on a small evaluation-size board takes wide copper traces to the exposed pads, exposed copper on the component side, thermal vias from the pad to a wide middle-layer ground plane and, perhaps, exposed copper on the solder side.
What the datasheet shows
Silergy’s typical-performance pages cover this circuit at 25 °C, 12 V in and 5 V out, with L = 4.7 µH, COUT = 66 µF, CFF = 220 pF and RFF = 1 kΩ. They include efficiency against load current from 1 mA to 6 A for the four output voltages, each with its own inductor (1.0, 3.3, 4.7 and 6.8 µH) and at several input voltages up to 28 V, start-up and shut-down from both VIN and EN at 6 A, load-transient steps (0.6 to 6 A and 0 to 3 A), output ripple at no load and at 6 A, and Bode plots for 1.2 V, 3.3 V, 5 V and 12 V outputs.
Reading the 5 V out curves by eye at 12 V in: efficiency is about 73% at 1 mA, about 89% at 10 mA, about 93% at 0.1 A and about 95% at 1 A, peaks near 96% around 3 A, and is about 94% at 6 A. At 28 V in the curve starts near 50% at 1 mA, reaches about 88% at 0.1 A and about 94% at 4–6 A. Treat these as rough, about two points either way, since they come from a graph.
Things to watch
- Treat 6 A as a ceiling. The datasheet’s formula puts the typical output current limit at about 6.6 A, and gives no minimum. See the worked example.
- Size the input capacitance for the load, not just the minimum. At 6 A the input capacitor carries about 3 A RMS and, with a single 10 µF ceramic, about 292 mV of ripple at 12 V in. The 10 µF figure in the datasheet is a floor.
- The 12 V row leaves less margin on the output capacitors. The datasheet asks for 16 V-rated capacitors, and at 12 V, ceramics of that rating can lose a large share of their capacitance to DC bias. That is our note, not the datasheet’s: check the effective capacitance on the capacitor’s DC-bias curve, and consider a higher voltage rating, before relying on the table’s ripple and feedforward values.
- Check the thermal budget. At 6 A and about 94% efficiency (from the 12 V in, 5 V out curve) the converter as a whole dissipates about 1.9 W, of which some is in the inductor. On the datasheet’s large four-layer board at 22 °C/W, even if all of it were in the IC, that is about 42 °C of rise. A smaller board will do worse, so use the datasheet’s derating curve and its layout advice.
- The inductor part number differs between the table and a plot. The 1.0 µH inductor is PCMB104T-1R0MT in the recommended-values table and PCMB104T-1R0MS in the efficiency plot’s title. Confirm the exact part number against Cyntec’s catalog before ordering.
- AGND and GND are separate pins joined at one point. Follow the layout rule about the single Kelvin connection at CVCC, or switching noise can reach the analog ground.
- At light load the frequency can drop into the audible range. If the converter sits near an audio path, test it with no load before committing to the design.
Documents
- SY21219 datasheet, Rev 1.0 (June 2025): the source of every value above unless marked as calculated
- SY21219 part page: specifications, recommended values and ordering information
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